Efficient VLSI Architectures for FIR Filters

The Finite Impulse Response (FIR) filters are widely used in many Digital Signal Processing (DSP) applications. For these applications, the low power, less area, high speed and low complexity FIR filter architectures are required. The researchers have proposed many FIR filters to meet the above design specifications. This paper is focused on the some efficient reconfigurable FIR filter architectures. The author Mohanthy et. al introduced a FIR filter architecture implemented for higher order fixed and reconfigurable applications. This filter is a block FIR filter, which realized in transpose-form configuration with less area, low power and less delay for large order filters. The second filter architecture in this paper is a custom reconfigurable power efficient FIR filter using multiplier less (Reduced Adder Graph) RAG-N Algorithm. In this method, the multiplier is realized using adders and shifters. This architecture is easy to implement, symmetrical and stable system. The next approach in this paper is implementation energy efficient FIR filter using alternative adders. In this, the filters are optimized for low power using multiplier less Multiple Constant Multiplication (MCM) algorithm. The alternative adder circuits are truncated and approximated to reduce the power consumption. Another efficient programmable FIR filter is implemented using Karatsuba Multiplication Algorithm. In this architecture, a parallel, modified booth pre-encoded, carry save Wallace tree multiplier is used for the multiplication of large numbers. This architecture is more efficient in terms of power, area and speed comparatively than other FIR filters. Finally, the comparison is taken place among the four efficient Very Large Scale Integration (VLSI) FIR filter architectures in terms of power, area and speed.